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Quad 7 ns Single Supply Comparator AD8564
FEATURES
5 V single-supply operation 7 ns propagation delay Low power Separate input and output sections TTL/CMOS logic-compatible outputs Wide output swing TSSOP, SOIC, and PDIP packages
PIN CONFIGURATIONS
-IN A +IN A GND OUT A OUT B V-ANA +IN B -IN B 1 16 -IN D +IN D V+ANA OUT D OUT C V+DIG +IN C -IN C
AD8564
8
9
Figure 1. 16-Lead TSSOP (RU-16)
-IN A +IN A GND OUT A OUT B V-ANA +IN B -IN B -IN D +IN D V+ANA OUT D OUT C V+DIG
01103-001
APPLICATIONS
High speed timing Line receivers Data communications High speed V-to-F converters Battery operated instrumentation High speed sampling systems Window comparators PCMCIA cards Upgrade for MAX901 designs
+IN C -IN C
AD8564
Figure 2. 16-Lead Narrow Body SOIC (R-16)
-IN A 1 +IN A 2
+- -+
14 13 16 15
-IN D +IN D V+ANA OUT D OUT C V+DIG +IN C -IN C
01103-002
GND 3 OUT A 4 OUT B 5 V-ANA 6 +IN B 7 -IN B 8
AD8564
+- -+
12 11 10 9
Figure 3. 16-Lead PDIP (N-16)
GENERAL DESCRIPTION
The AD8564 is a quad 7 ns comparator with separate input and output supplies, thus enabling the input stage to be operated from 5 V dual supplies or a 5 V single supply while maintaining a CMOS-/TTL-compatible output. Fast 7 ns propagation delay makes the AD8564 a good choice for timing circuits and line receivers. Independent analog and digital supplies provide excellent protection from supply pin interaction. The AD8564 is pin compatible with the MAX901 and has lower supply currents. All four comparators have similar propagation delays. The propagation delay for rising and falling signals is similar, and tracks over temperature and voltage. These characteristics make the AD8564 a good choice for high speed timing and data communications circuits. For a similar single comparator with latch function, refer to the AD8561 data sheet. The AD8564 is specified over the industrial temperature range (-40C to +125C). The quad AD8564 is available in the 16-lead TSSOP, 16-lead narrow body SOIC, and 16-lead plastic DIP packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1999-2007 Analog Devices, Inc. All rights reserved.
01103-003
AD8564 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configurations ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Specifications............................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution...................................................................................5 Typical Performance Characteristics ..............................................6 Applications Information .................................................................9 Optimizing High Speed Performance ........................................9 Output Loading Considerations..................................................9 Input Stage and Bias Currents .....................................................9 Using Hysteresis ......................................................................... 10 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 12
REVISION HISTORY
8/07--Rev. A to Rev. B Updated Format..................................................................Universal Changes to Applications .................................................................. 1 Changes to General Description .................................................... 1 Changes to Specifications ................................................................ 3 Changes to the Absolute Maximum Ratings Section .................. 5 Changes to the Applications Information Section ....................... 9 Deleted Spice Model Section......................................................... 11 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 13 6/99--Rev. 0 to Rev. A
Rev. B | Page 2 of 12
AD8564 SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
V+ANA = V+DIG = 5.0 V, V-ANA = 0 V, TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance DIGITAL OUTPUTS Logic 1 Voltage Logic 0 Voltage DYNAMIC PERFORMANCE 2 Propagation Delay Symbol VOS -40C TA +125C 1 VOS/T IB IOS VCM CMRR AVO CIN VOH VOL tP 4 VCM = 0 V -40C TA +125C1 VCM = 0 V 0 V VCM 3.0 V RL = 10 k 0 65 85 3000 3.0 3.5 0.3 6.75 8 0.5 3.8 1.5 80 10.5 4 9 3 2.75 Conditions Min Typ 2.3 Max 7 8 Unit mV mV V/C A A A V dB V/V pF V V ns ns ns ns ns ns dB mA mA mA mA mA mA mA mA
IOH = -3.2 mA, VIN > 250 mV IOL = 3.2 mA, VIN > 250 mV 200 mV step with 100 mV overdrive -40C TA +125C1 100 mV step with 5 mV overdrive 100 mV step with 20 mV overdrive 20% to 80% 20% to 80%
2.4
0.4 9.8 13 2.0
Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio Analog Supply Current
tP
PSRR I+ANA
4.5 V V+ANA and V+DIG 5.5 V -40C TA +85C1 -40C TA +125C1 VO = 0 V, RL = -40C TA +125C1 -40C TA +85C1 -40C TA +125C1
Digital Supply Current Analog Supply Current
IDIG I-ANA
6.0 -7.0
14.0 15.6 17 7.0 8.0 +14.0 15.6 17
1 2
Full electrical specifications to -55C, but these package types are guaranteed for operation from -40C to +125C only. Package reliability below -40C is not guaranteed. Guaranteed by design.
Rev. B | Page 3 of 12
AD8564
V+ANA = V+DIG = 5.0 V, V-ANA = -5 V, TA = 25C, unless otherwise noted. Table 2.
Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance DIGITAL OUTPUTS Logic 1 Voltage Logic 0 Voltage DYNAMIC PERFORMANCE 2 Propagation Delay Symbol VOS -40C TA +125C 1 VOS/T IB IOS VCM CMRR AVO CIN VOH VOL tP 4 VCM = 0 V -40C TA +125C1 VCM = 0 V 0 V VCM 3.0 V RL = 10 k -4.9 65 85 3000 3.0 3.6 0.2 6.75 8 8 0.5 3 3 50 70 10.8 4 9 3 +3.5 Conditions Min Typ 2.3 Max 7 10 Unit mV mV V/C A A A V dB V/V pF V V ns ns ns ns ns ns dB mA mA mA mA mA mA mA mA
IOH = -3.2 mA, VIN > +250 mV IOL = 3.2 mA, VIN > 250 mV 200 mV step with 100 mV overdrive -40C TA +85C1 100 mV step with 5 mV overdrive 100 mV step with 20 mV overdrive 20% to 80% 20% to 80%
2.6
0.3 9.8 13 2.0
Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY Power Supply Rejection Ratio Analog Supply Current
tP
PSRR I+ANA
4.5 V V+ANA and V+DIG 5.5 V -40C TA +85C1 -40C TA +125C1 VO = 0 V, RL = -40C TA +125C1 -40C TA +85C1 -40C TA +125C1
Digital Supply Current Analog Supply Current
IDIG I-ANA
3.6 -8.2
14.0 15.6 17 4.4 5.6 +14.0 15.6 17
1 2
Full electrical specifications to -55C, but these package types are guaranteed for operation from -40C to +125C only. Package reliability below -40C is not guaranteed. Guaranteed by design.
Rev. B | Page 4 of 12
AD8564 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Total Analog Supply Voltage Digital Supply Voltage Analog Positive Supply to Digital Positive Supply Input Voltage1 Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range (Soldering, 10 sec)
1
THERMAL RESISTANCE
Rating 14 V 17 V -600 mV 7 V 8 V Indefinite -65C to +150C -55C to +125C -65C to +150C 300C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages (SOIC and TSSOP). JA is specified for device in socket for PDIP. Table 4. Thermal Resistance
Package Type 16-Lead PDIP (N) 16-Lead Narrow Body SOIC (R) 16-Lead TSSOP (RU) JA 90 113 180 JC 47 37 37 Unit C/W C/W C/W
The analog input voltage is equal to 7 V or the analog supply voltage, whichever is less.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. B | Page 5 of 12
AD8564 TYPICAL PERFORMANCE CHARACTERISTICS
V+ANA = V+DIG = 5 V, V-ANA = 0 V, TA = 25C, unless otherwise noted.
1.0 500
INPUT OFFSET VOLTAGE (mV)
0.8 NUMBER OF AMPLIFIERS
01103-004
400
0.6
300
0.4
200
0.2
100
-50
-25
0
25
50
75
100
125
150
-5
-4
-3
-2
-1
0
1
2
3
4
5
TEMPERATURE (C)
INPUT OFFSET VOLTAGE (mV)
Figure 4. Input Offset Voltage vs. Temperature
0
10
Figure 7. Input Offset Voltage Distribution
STEPSIZE = 100mV OVERDRIVE = 5mV
-1
8
INPUT BIAS CURRENT (A)
PROPAGATION DELAY (ns)
tPDHL
6
-2
tPDLH
-3
4
-4
2
01103-005
-50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. Input Bias Current vs. Temperature
0 V+ANA = V+DIG = +5V V-ANA = -5V
OUTPUT HIGH VOLTAGE (mV)
Figure 8. Propagation Delay, tPDHL/tPDLH vs. Temperature
5.0
-1
INPUT BIAS CURRENT (A)
4.4 TA = +85C 3.8 TA = +25C 3.2
-2
-3
-4
2.6
TA = -40C
01103-006
-5.0
-2.5
0
2.5
5.0
0
3
INPUT COMMON-MODE VOLTAGE (V)
6 9 SOURCE CURRENT (mA)
12
15
Figure 6. Input Bias Current vs. Input Common-Mode Voltage
Figure 9. Output High Voltage, VOH vs. Source Current
Rev. B | Page 6 of 12
01103-009
-5 -7.5
2.0
01103-008
-5 -75
0 -50
01103-007
0 -75
0
AD8564
0.5
3.0
TA = -40C 0.3 TA = +25C
I+DIG SUPPLY CURRENT (mA)
OUTPUT LOW VOLTAGE (V)
0.4
2.5
2.0 TA = +25C 1.5 TA = +85C
0.2 TA = +85C 0.1
1.0 TA = -40C 0.5
01103-010
0
3
6
9
12
15
2
4
6
8
10
12
SINK CURRENT (mA)
V+DIG SUPPLY VOLTAGE (V)
Figure 10. Output Low Voltage, VOL vs. Sink Current
5
Figure 13. I+DIG Supply Current/Comparator vs. V+DIG Supply Voltage
5
I+ANA SUPPLY CURRENT (mA)
TA = +85C 3 TA = +25C 2
I+ANA SUPPLY CURRENT (mA)
4
4 V+ANA = 5V 3 V+ANA = +5V 2
TA = -40C
1
1
01103-011
2
4
6
8
10
12
-50
-25
V+ANA SUPPLY VOLTAGE (V)
0 25 50 75 TEMPERATURE (C)
100
125
150
Figure 11. I+ANA Supply Current/Comparator vs. V+ANA Supply Voltage
0
Figure 14. I+ANA Supply Current/Comparator vs. Temperature
0
I-ANA SUPPLY CURRENT (mA)
TA = -40C TA = +25C
I-ANA SUPPLY CURRENT (mA)
-1
-1 V+ANA = +5V -2 V+ANA = 5V -3
-2 TA = +85C -3
-4
-4
2
4
6
8
10
12
01103-012
-50
-25
0
25
50
75
100
125
150
V-ANA SUPPLY VOLTAGE (V)
TEMPERATURE (C)
Figure 12. I-ANA Supply Current/Comparator vs. V-ANA Supply Voltage
Figure 15. I-ANA Supply Current/Comparator vs. Temperature
Rev. B | Page 7 of 12
01103-015
-5
-5 -75
01103-014
0
0 -75
01103-013
0
0
AD8564
2.0
I+DIG SUPPLY CURRENT (mA)
1.5
1.0
0.5
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
Figure 16. I+DIG Supply Current/Comparator vs. Temperature
01103-016
0 -75
Rev. B | Page 8 of 12
AD8564 APPLICATIONS INFORMATION
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator or amplifier, proper design and layout techniques should be used to ensure optimal performance from the AD8564. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from the source to the input is an important consideration in maximizing the high speed operation of the AD8564. Source resistance, in combination with equivalent input capacitance, may cause a lagged response at the input, thus delaying the output. The input capacitance of the AD8564, in combination with stray capacitance from an input pin to ground, may result in several picofarads of equivalent capacitance. A combination of 3 k source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is slower than the 5 ns capability of the AD8564. Source impedances should be less than 1 k for the best performance. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 F electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible to the power supply pins to ground. These capacitors act as a charge reservoir for the device during high frequency switching. A ground plane is recommended for proper high speed performance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary current paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused from ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board.
OUTPUT LOADING CONSIDERATIONS
The AD8564 output can deliver up to 40 mA of output current without any significant increase in propagation delay. The output of the device should not be connected to more than 20 TTL input logic gates or drive a load resistance less than 100 . To ensure the best performance from the AD8564, it is important to minimize capacitive loading of the output of the device. Capacitive loads greater than 50 pF cause ringing on the output waveform and reduce the operating bandwidth of the comparator. Propagation delay also increases with capacitive loads above 100 pF.
INPUT STAGE AND BIAS CURRENTS
The AD8564 uses a PNP differential input stage that enables the input common-mode range to extend all the way from the negative supply rail to within 2.2 V of the positive supply rail. The input common-mode voltage can be found as the average of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken to not allow the input common-mode voltage to exceed this voltage. The input bias current for the AD8564 is 4 A. As with any PNP differential input stage, this bias current goes to 0 on an input that is high and doubles on an input that is low. Care should be taken in choosing resistor values to be connected to the inputs because large resistors could cause significant voltage drops due to the input bias current. The input capacitance for the AD8564 is typically 3 pF. This can be measured by inserting a large source resistance to the input and measuring the change in propagation delay.
Rev. B | Page 9 of 12
AD8564
USING HYSTERESIS
Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desirable for the output to toggle between states when the input signal is near the switching threshold. Figure 17 shows a method for configuring the AD8564 with hysteresis.
COMPARATOR SIGNAL
voltage is greater than VHI and does not switch low again until the input voltage is less than VLO, as given in Equation 2.
VHI = (V+ - 1 - VREF ) R1 VREF R1 + R2
(1)
R1 VLO = VREF 1 - R1 + R2 where V+ is the positive supply voltage. The CF capacitor may also be added to introduce a pole into the feedback network. This has the effect of increasing the amount of hysteresis at high frequencies. This can be useful when comparing a relatively slow signal in a high frequency noise environment. At frequencies greater than f P =
(2)
VREF
R1
R2
01103-017
CF
Figure 17. Configuring the AD8564 with Hysteresis
The input signal is connected directly to the inverting input of the comparator. The output is fed back to the noninverting input through R2 and R1. The ratio of R1 to R1 + R2 and the output swing establishes the width of the hysteresis window, with VREF setting the center of the window or the average switching voltage. The output switches high when the input
1 , the hysteresis 2CF R2 window approaches VHI = V+ - 1 V and VLO = 0 V.
At frequencies less than fP, the threshold voltages remain as it is in Equation 1.
Rev. B | Page 10 of 12
AD8564 OUTLINE DIMENSIONS
0.800 (20.32) 0.790 (20.07) 0.780 (19.81)
16 1 9
8
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.015 (0.38) MIN 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
0.005 (0.13) MIN
COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown in inches and (millimeters)
10.00 (0.3937) 9.80 (0.3858)
16 1 9 8
4.00 (0.1575) 3.80 (0.1496)
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
1.75 (0.0689) 1.35 (0.0531) SEATING PLANE
0.50 (0.0197) 0.25 (0.0098) 8 0 1.27 (0.0500) 0.40 (0.0157)
45
0.25 (0.0098) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060606-A
Figure 19. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches)
Rev. B | Page 11 of 12
073106-B
AD8564
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8564AN AD8564ANZ 1 AD8564AR AD8564AR-REEL AD8564AR-REEL7 AD8564ARZ1 AD8564ARZ-REEL1 AD8564ARZ-REEL71 AD8564ARU-REEL AD8564ARUZ-REEL1
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP]
Package Option N-16 N-16 R-16 R-16 R-16 R-16 R-16 R-16 RU-16 RU-16
Z = RoHS Compliant Part.
(c)1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01103-0-8/07(B)
Rev. B | Page 12 of 12

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